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smm665b preliminary information 1 (see last page) ? summit microelectronics, inc. 2006 ? 757 n. mary avenue ? sunnyvale ca 94085 ? phone 408 523-1000 ? fax 408 523-1266 the summit web site can be accessed by ?right? or ?left? mouse clicking on the link: http://www.summitmicro.com/ 2089 2.0 4/11/2007 1 six-channel active dc output controller, monitor, marginer and sequencer features & applications ? extremely accurate (0.2%) active dc output control (adoc tm ) ? undervoltage lockout function (uvlo) ? adoc tm automatically adjusts supply output voltage level under all dc load conditions ? monitors, controls, sequences and margins up to six supplies from 0.3v to 5.5v with 1.25v vref wide margin/adoc range from 0.3v to vdd ? programmable power-on/-off sequencing ? monitors internal temperature sensor ? operates from any intermediate bus supply from 8v to 15v and from 2.7v to 5.5v ? monitors 12v input and vdd ? monitors two general-purpose 10-bit adc inputs ? programmable threshold limits (2 ov/2 uv) for each monitored input ? programmable reset, healthy and fault ? 4k-bit general purpose nonvolatile memory ? i 2 c 2-wire serial bus for programming configuration and monitoring status, including 10-bit adc conversion results applications ? monitor/control distributed and pol supplies ? multi-voltage processors, dsps, asics used in telecom, compactpci or server systems introduction the smm665b is an active dc output power supply controller (adoc tm ) that monitors, margins and cascade sequences. the adoc feature is unique and maintains extremely accurate settings of system supply voltages to within 0.2% under full load. the device actively controls up to six dc/dc converters that use a trim or regulator vadj/fb pin to adjust the output voltage. for system te st, the part also controls margining of the supplies using i 2 c commands. it can margin supplies with either positive or negative control within a range of 0.3v to vdd depending on the specified range of the conv erter. the smm665b also intelligently sequences or cascades the power supplies on and off in any order using enable outputs with programmable polarity. it can operate off any intermediate bus supply ranging from 8v to 15v or from 5.5v to as low as 2.7v. the part monitors six power supply channels as well as vdd, 12v input, two general-purpose analog inputs and an internal temperature sensor using a 10-bit adc. the 10-bit adc can measure the value on any one of the monitor channels and output the data via the i 2 c bus. a host system can communicate wi th the smm665b status register, optionally control power-on/off, margining and utilize 4k-bits of nonvolatile memory. simplified applications drawing trim b pup b vm b trim_cap b cap b trim a pup a vm a trim_cap a cap a smm665b p/ asic vdd rst healthy mr 3.3vin (+2.7v to +5.5v range) reset ready healthy 12vin 12vin (+8v to +15v range) external or internal temp sensor ain1 vref_adc 2.5vin 1.2vin 12v sda scl i 2 c bus 3.3v a2 vref_cntl vin trim vout dc/dc converter a on/off vin trim vout dc/dc converter b on/off external or internal reference environ mental sensor ain2 dc/dc converter c, e dc/dc converter d, f 2 of 6 dc-dc converters shown figure 1 ? applications schematic using the smm665b controller to actively cont rol the output levels of up to six dc/dc converters while also providing power on/off, cascade sequencing and output margining. note: this is an applications example only. some pins, components and values are not shown.
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 2 general description the smm665b is a highly integrated and accurate power supply controller, monitor and sequencer. it has the ability to automatically control, monitor and cascade sequence up to six power supplies. also, the smm665b can monitor the vdd input, the 12v input, two general-purpose analog inputs and the internal temperature sensor. the smm665b has four operating modes: power-on sequencing mode, monitor mode, supply margining mode using active dc output control (adoc tm ), and power-off sequencing mode. power-on sequencing can be initiated via the pwr_on/off pin or i 2 c control. in this mode, the smm665b will sequence the power supply channels on in any order by activating the pup outputs and monitoring the respective converter voltages to ensure cascading of the supplies. cascade sequencing is the ability to hold off the next sequenced supply until the first supply reaches a pr ogrammed threshold. a programmable sequence termination timer can be set to disable all channels if the power-on sequence stalls. once all supplies have sequenced on and the voltages are above the uv settings, the active dc control, if enabled, will bring the supply voltages to their nominal settings. during this mode, the healthy output will remain inactive and the rst output will remain active. once the power-on sequencing mode is complete, the smm665b enters monitor mode. in the monitor mode, the smm665b starts the adoc control of the supplies and adjusts the output voltage to the programmed setting under all load conditions, especially useful for supplies without sense lines. typical converters have 2% accuracy ratings for their output voltage, the active dc output control feature of the smm665b increases the accuracy to 0.2% (using a 0.1% external voltage reference). the part also enables the triggering of outputs by monitored fault conditions. the 10-bit adc cycles through all 11 channels every 2ms and checks the conversions against the programmed threshold limits. the results can be used to trigger rst, healthy and fault outputs as well as to trigger a power-off or a force shutdown operation. while the smm665b is in its monitoring mode, an i 2 c command to margin the supply voltages can bring the part into margining mode. in margining mode the smm665b can margin six supply voltages in any combination of nominal, high and low voltage settings using the adoc feature, all to within 0.2% using a 0.1% external reference. the margin high and low voltage settings can range from 0.3v to vdd around the converters? nominal output voltage setting depending on the specified margin range of the dc- dc converter. during this mode the healthy output is always active and the rst output is always inactive regardless of the voltage threshold limit settings and triggers. furthermore, the triggers for power-off and force shutdown are temporarily disabled. the power-off sequencing mode can only be entered while the smm665b is in the monitoring mode. it can be initiated by either bringing the pwr_on/off pin inactive, through i 2 c control or triggered by a channel exceeding its programmed thresholds. once power- off is initiated, it will disable the active dc control and sequence the pup outputs off in either the same or reverse order as power-on sequencing and monitor the supply voltages to ensure cascading of the supplies as they turn off. the sequence termination timer can be programmed to immediately disable all channels if the power-off sequencing stalls. the rst output will remain active throughout this mode while the healthy output remains inactive. figure 2 ? example power supply sequencing and system start-up initialization using the smm665b. any order of supply sequencing can be applied using the smm665b. power supply ordering, trimming and active dc control allows supply cascade sequencing, automatic le vel adjustment, margin t esting and reset control. 2.5v 2.7v 1.8v 2.0v 1.5v vdd (+2.7v to +5.5v) or 12vin ( +8v to +15v) rst# --- t1 ---
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 3 ain 2 10-bit adc vref_adc ain 1 vm a active dc control (adoc tm ) cap a vm f cap f trim a trim_cap a trim f trim_cap f vref_cntl filt_cap 12vin vdd pup a cascade sequence control pup b pup c pup d pup e pup f fs pwr_on/off 3.6v or 5.5v regulator power supply arbitrator temperature sensor vdd_cap output control mr rst healthy fault memory, limit and status registers i 2 c interface sda scl a2 gnd uvlo control figure 3 ? smm665b internal functional block diagram. internal functional block diagram
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 4 pin number pin type pin name pin description 1 data sda i 2 c bi-directional data line 2 clk scl i 2 c clock line 3 in a2 the address pin is biased either to vdd_cap or gnd. when communicating with the smm665b over the 2-wire bus a2 provides a mechanism for assigning a unique bus address. 4 in mr programmable active high/low input. when asserted the rst output will be go active. when de-asserted the rst output will go inactive immediately after a reset timeout period (t prto ) if there are no rst trigger sources active. this timeout period makes it suitable to use a pushbutton for manual reset. 5 in pwr_on/off programmable active high/low input signals the start of the power sequencing. when asserted the part will sequence the supplies on and when de-asserted the part will sequence the supplies off. note: the smm665b does not monitor for faults during sequencing. the pwr_on/off pin is overridden by the i 2 c power on/off command. to get the pin to work again requires the part be given an i 2 c 'clear' command (see page 16, ?restart of power-on cascade sequencing?). 6 in fs programmable active high/low input. fo rce shutdown is used to immediately turn off all converter enable signals (pup outputs) when a fault is detected. 7 out fault programmable active high/low open drain fault output. active when a programmed fault condition exists on ain1 , ain2, or the internal temperature sensor. 8 out healthy programmable active high/low open drai n healthy output. active when all programmed power supply inputs and monitored inputs are within ov and uv limits. 9 out rst programmable active high/low open drain reset output. active when a programmed fault condition exists on any power supply inputs or monitored inputs or when mr is active. rst has a programmable timeout period with options for 0.64ms, 25ms, 100ms and 200ms. 10 in ain1 general purpose monitored analog input 11 in ain2 general purpose monitored analog input 12 gnd gnd ground 13 in vref_adc voltage reference input used for a/d conversion where: (4xvref_adc) = full scale (fs) for vm a-f and vdd (12xvref_adc) = fs for 12vin (2xvref_adc) = fs for ain1 and ain2. vref_adc can be connected to vref_cntl in most applications. pin descriptions
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 5 pin number pin type pin name pin description 14 i/o vref_cntl voltage reference input used for dc output control and margining. vref_cntl can be programmed to output the internal 1.25v reference. 15 cap filt_cap external capacitor input used to filter vm x inputs 41,36, 31,26, 21,16 in vm x positive converter sense line, vm a through vm f 42,37, 32,27, 22,17 cap cap x external capacitor input used to filter the vm x inputs to the 10-bit adc, cap a through cap f . this provides an rc filter where r = 25k ? . 43,38, 33,28, 23,18 out pup x programmable active high/low open drain converter enable output, pup a through pup f 44,39, 34,29, 24,19 out trim x output voltage used to control t he output of dc/dc converters, trim a through trim f . if the adoc/margining functionality is not used on a channel the associated trim x pin should be left floating 45,40, 35,30, 25,20 cap trim_cap x external sample and hold capacitor input used to set the voltage on the trim pins, trim_cap a through trim_cap f 46 pwr vdd power supply of the part 47 pwr 12vin 12v power supply input internally r egulated to either 3.6v or 5.5v 48 cap vdd_cap external capacitor input used to filter the internal supply pin descriptions ( cont. )
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 6 package and pin configuration 48 lead tqfp 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 sda scl a2 mr pwr_on/off fs fault healthy rst ain1 ain2 gnd vref_adc vref_cntl filt_cap vmf capf pupf trimf trim_capf vme cape pupe trime vmb trim_capc trimc pupc capc vmc trim_capd trimd pupd capd vmd trim_cape vdd_cap 12vin vdd trim_capa trima pupa capa vma trim_capb trimb pupb capb
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 7 recommended operating conditions absolute maximum ratings temperature un der bias....................... -55 c to 125 c storage temper ature............................ -65 c to 150 c terminal voltage with respect to gnd: vdd supply voltage ......................... -0.3v to 6.0v 12vin supply voltage ..................... -0.3v to 15.0v pup a , through pup f ....................... -0.3v to 15.0v all others ................................ -0.3v to v dd + 0.7v output short circ uit current ............................... 100ma lead solder temperat ure (10 secs) .................... 300 c junction temperat ure.......................?? .....?...150c esd rating per jedec???????....??..2000v latch-up testing per jedec???..?....?? 100ma note - the device is not guaranteed to function outside its operating rating. stresses listed under absolute maxi mum ratings may cause permanent damage to the device. these are stre ss ratings only and functional operation of the device at t hese or any other conditions outside those lis ted in the operational sections of t he specification is not implied. exposure to any absolute maximum rating for extended per iods may affect device performance and reliability. devices are esd s ensitive. handling precautions are recommended. temperature range (industrial)...........?40 c to +85 c (commercial) ............?5 c to +70 c vdd supply voltage .................................. 2.7v to 5.5v 12vin supply voltage 1 ............................8.0v to 14.0v vin ............................................................ gnd to vdd vout ...................................................... g nd to 14.0v package thermal resistance ( ja ) 48 lead tqfp????????????.?80 o c/w moisture classification level 1 (msl 1) per j-std- 020. msl 3 for 100% sn, rohs compliant, see ordering information. note 1 ? range depends on internal regulator set to 3.6v or 5.5v, see 12vin specification below. reliability characteristics data retention??????????..?..100 years endurance????????.???.100,000 cycles dc operating characteristics (over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd.) symbol parameter notes min typ max unit vdd supply voltage 2.7 5.5 v internally regulated to 5.5v 10 14 v 12vin supply voltage internally regulated to 3.6v 6 14 v i dd power supply current from vdd all trim pins floating, 12vin floating 3 5 ma i 12vin power supply current from 12vin all trim pins floating, vdd floating 3 5 ma trim characteristics trim sourcing maximum current 1.5 ma i trim trim output current through 100 ? to 1.0v trim sinking maximum current 1.5 ma v trim margin control and adoc range depends on trim range of dc-dc converter vref_cnt l/4 vdd v trim_cap characteristics i trim _ cap trim output current through 1uf capacitor to ground max acceptable board and cap leakage is 50 na 2 100 na all other input and output characteristics internally regulated to 3.6v 3.4 3.6 3.8 v internally regulated to 5.5v 5.3 5.5 5.7 v v vdd_cap vdd_cap voltage no voltage on 12vin vdd - 0.1 vdd vdd + 0.1 v
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 8 dc operating characteristics (continued) (over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd.) symbol parameter notes min typ max unit vdd = 2.7v 0.7 x vdd_cap v v ih input high voltage (fs, pwr_on/off, mr#, sda, scl) 3 vdd = 5.0v 0.7 x vdd_cap v vdd = 2.7v 0.3 x vdd_cap v v il input low voltage (fs, pwr_on/off, mr#, sda, scl) 3 vdd = 5.0v 0.3 x vdd_cap v internally regulated to 3.6v 0.7 x vdd_cap v v ih input high voltage (fs, pwr_on, mr#, sda, scl) 3 internally regulated to 5.5v 0.7 x vdd_cap v internally regulated to 3.6v 0.3 x vdd_cap v v il input low voltage (fs, pwr_on, mr#, sda, scl) 3 internally regulated to 5.5v 0.3 x vdd_cap v i ol output low current 6 note ? total i sink from all pupx pins should not exceed 6ma or adoc acc specification will be affected 0 1.0 ma i olsda output low current for sda vol=0.4v 3 ma i s leakage current on sda and scl when sda or scl are at 3.6v 1.0 a v sense positive sense voltage vm pin +0.3 vdd_cap v v monitor monitor threshold step size vm, ain1/ain2 pins 5 mv commercial temp range -4 +4 o c t sa internal temperature sensor accuracy 5 industrial temp range -6 +6 o c t monitor temperature threshold step size internal temp sensor 0.25 o c v ref internal 1.25v ref output voltage 1.24 1.25 1.26 v ?40 c to +85 c -0.25 +0.25 % v ref tc internal v ref temperature coefficient ?5 c to +70 c -0.15 +0.15 % v ref acc internal v ref accuracy -0.4 +0.4 % ext v ref external v ref voltage range 0.5 vdd_cap v external v ref =1.25v, 0.1%, total pupx i sink = 6ma, v sense 3.5v -0.2 0.1 +0.2 % external v ref =1.25v, 0.1%, total pupx i sink = 6ma, v sense 3.5v -0.5 0.3 +0.5 % adoc acc adoc/margin accuracy internal v ref =1.25v, total pupx i sink = 6ma -0.5 0.3 +0.5 % v out_valid minimum output valid voltage vdd_cap voltage at which the pup, rst, healthy and fault outputs are valid 1 v
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 9 dc operating characteristics (continued) (over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd.) ain1/ain2 adc characteristics symbol parameter notes min typ max unit n resolution 10 bits mc missing codes minimum resolution for which no missing codes are guaranteed 10 bits s/n signal-to-noise ratio conversion rate = 500hz 72 db dnl differential non-linearity -1/2 +1/2 lsb inl integral non-linearity note 7 -1 +1 lsb gain positive full scale gain error note 7 -0.5 +0.5 % offset offset error note 7 -1 +1 lsb adc_tc full scale temperature coefficient 15 ppm/ o c im adc analog adc input impedance 10 m ? ii vref v ref input current 250 na ic vref v ref input capacitance 200 pf ir vref v ref input impedance 1 k ? vma-vmf, vdd adc characteristics symbol parameter notes min typ max unit n resolution 10 bits mc missing codes minimum resolution for which no missing codes are guaranteed 10 bits s/n signal-to-noise ratio conversion rate = 500hz 72 db err_adc total adc error total adc read error -4 +4 lsb im adc analog adc input impedance vma-vmf 100 k ? 12vin adc characteristics symbol parameter notes min typ max unit n resolution 10 bits mc missing codes minimum resolution for which no missing codes are guaranteed 10 bits s/n signal-to-noise ratio conversion rate = 500hz 72 db err_adc total adc error total adc read error -4 +4 lsb note 1 ? range depends on internal regulator set to 3.6v or 5.5v see 12vin specification. note 2 ? see application note 37 which describes the type of capacitors to use to obtain minimum leakage. note 3 ? all logic levels are with respect to the voltage on v dd_cap, when supplied from vdd; vdd_cap is equal to vdd, under no load. note 4 ? (100mv typical hysteresis) note 5 ? under certain operating condi tions, self-heating could result in additional temperature sensor error. note 6 ? sda not included (separat e electrical specification) note 7 ? the formula for the total adc inaccuracy is: [((adc read voltage) +/- inl)*(range of gain error)]+range of offset erro r
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 10 ac operating characteristics over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd. see figure 5 and 6 timing diagrams. symbol description conditions min typ max unit t dpon = 0.64ms t dpon = 12.5ms t dpon = 25ms t dpon programmable power-on delay from vm x out-of-fault to pup y active t dpon = 50ms -15 t dpon +15 % t dpoff = 0.64ms t dpoff = 12.5ms t dpoff = 25ms t dpoff programmable power-off delay from vm x off to pup y inactive t dpoff = 50ms -15 t dpoff +15 % t prto = 0.64ms t prto = 25ms t prto = 100ms t prto programmable reset time-out period t prto = 200ms -15 t prto +15 % t stt = off t stt = 100ms t stt = 200ms t stt programmable sequence termination timer t stt = 400ms -15 t stt +15 % t adc 10-bit adc sampling period time for adc conversion of all 11 channels 2 ms t dc_control active dc control sampling period update period for active dc control of channels a ? f 1.7 ms t conv single adc channel conversion time update period for active dc control per channel 182 s slow margin, + 10% change in voltage with 0.1% ripple trim_cap=1 f 850 ms t margin margin time from nominal fast margin, + 10% change in voltage with 0.1% ripple trim_cap=1 f 85 ms
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 11 i 2 c 2-wire serial interface ac operating characteristics ? 100/400khz over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd. see figure 4 timing diagram. 100khz 400khz symbol description conditions min typ max min typ max units f scl scl clock frequency 0 100 0 400 khz t low clock low period 4.7 1.3 s t high clock high period 4.0 0.6 s t buf bus free time before new transmission - note 1 / 4.7 1.3 s t su:sta start condition setup time 4.7 0.6 s t hd:sta start condition hold time 4.0 0.6 s t su:sto stop condition setup time 4.7 0.6 s t aa clock edge to data valid scl low to valid sda (cycle n) 0.2 3.5 0.2 0.9 s t dh data output hold time scl low (cycle n+1) to sda change 0.2 0.2 s t r scl and sda rise time note 1 / 1000 1000 ns t f scl and sda fall time note 1 / 300 300 ns t su:dat data in setup time 250 150 ns t hd:dat data in hold time 0 0 ns ti noise filter scl and sda noise suppression 100 100 ns t wr_config write cycle time config configuration registers 10 10 ms t wr_ee write cycle time ee memory array 5 5 ms note: 1 / - guaranteed by design. t r t f t high t low t su:sda t hd:sda t su:dat t hd:dat t su:sto t buf t dh t aa scl sda (in) sda (out) t w r (for w rite operation only) figure 4 - basic i 2 c serial interface timing timing diagrams
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 12 figure 5 - the smm665b cascade sequencing the suppli es on and then monitoring for fault conditions. figure 6 - the smm665b cascade sequencing the supplies off. t dpona t dponb t dponc t dpond 012 vm a pup a pup b pup c pup d vm b vm c vm d timing diagrams (continued) t dpoffa t dpoffb t dpoffc t dpoffd 210 vm a pup a pup b pup c pup d vm b vm c vm d
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 13 applications information device operation power supply the smm665b can be powered by either a 12v input through the 12vin pin or by a 3.3v or 5.0v input through the vdd pin. the 12vin pin feeds an internal programmable regulator that internally generates either 5.5v or 3.6v. a voltage arbitration circuit allows the device to be powered by the highest voltage from either the regulator output or the vdd input. this voltage arbitration circuit c ontinuously checks for these voltages to determine which will power the smm665b. the resultant internal power supply rail is connected to the vdd_cap pin that allows both filtering and hold- up of the internal power supply. to ensure that the input voltage is high enough for reliable operation, an under voltage lockout circuit holds the controlled supplies off until the uvlo thresholds are met. modes of operation the smm665b has four basic modes of operation (shown in figures 5 through 8): power-on cascade sequencing mode, ongoing operations-monitoring mode, supply margining mode and power-off cascade sequencing mode. in addition, there are two features: adoc and forced shutdown which can be used during monitoring and margining mode. a detailed description of each mode and feature follows. active dc output control (adoc tm ) the smm665b can actively control the dc output voltage of bricks or dc/dc conv erters that have a trim pin during monitoring and margining mode. the converter may be an off-the shelf compact device, or may be a ?roll your own? circuit on the application board. in either case, the smm665b dramatically improves voltage accuracy (down to 0.2%) by implementing closed-loop adoc active control. this utilizes the dc-dc?s ?trim? pin as shown in figure 12, or an equivalent output voltage feedback adjustment ?vadj? or ?fb? node in a user?s custom circuit, figure 13. each of the trim x pins on the smm665b is connected to the trim input pins on the power supply converters. a sense line from the channel?s point-of- load connects to the corresponding vm input. the adoc function cycles through all six channels (a-f) every 1.7ms making slight adjustments to the voltage on the associated trim x output pins based on the voltage inputs on the vm x pins. these voltage adjustments allow the smm665b to control the output voltage of power supply converters to within 0.2% when using a 0.1% external voltage reference. figure 7 - waveform shows four smm665b channels exhibiting sequence-on to nominal voltage, margin high or low, nominal voltage and then sequence-off ch 1 = 2.5v dc-dc converter output (yellow trace) ch 2 = 1.8v dc-dc converter output (blue trace) ch 3 = 1.5v dc-dc converter output (purple trace) ch 4 = 1.2v dc-dc converter output (green trace figure 8 - waveform shows two smm665b channels sequencing-on to nominal voltage, margin high and low, and then sequence-off. channel 3 and 4 shows the rst and healthy signals. ch 1 = 2.5v dc-dc converter output (yellow trace) ch 2 = 1.5v dc-dc converter output (blue trace) ch 3 = rst signal output (purple trace) ch 4 = healthy signal output (green trace
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 14 a pulse of current, either sourced or sunk for 5s every 1.7ms, to the c apacitors connected to the trim_cap x pins adjusts the voltage output on the trim x pins. the voltages on the trim_cap x pins are buffered and applied to the trim x pins. the voltage adjustments on the trim x pins cause a slight ripple of less than 1mv on the power supply voltages. the amplitude of this ripple is a function of the trim_cap capacitor and the trim gain of the converter. application note 37 details the calculation of the trim_cap capacitor to achieve a desired minimum ripple. each channel can be programmed to either enable or disable the active dc control function. when disabled or not active, the trim x pins on the smm665b are high impedance inputs. if disabled and not used, they can be connected to ground. the voltages on the trim x pins are buffered and applied to the trim_cap x pins charging the capacitors. this allows a smooth transition from the converter powering up to its nominal voltage; to the smm665b controlling that voltage, and to the active dc control nominal setting. the pulse of current can be increased to a 10x pulse of current until the power s upply voltages are at their nominal settings by selecting the programmable speed-up convergence option. as the name implies, this option decreases the time required to bring a supply voltage from the converter?s nominal output voltage to the active dc control nominal voltage setting. power-on cascade sequencing the smm665b can be programmed to sequence up to six power supplies in any order. each of these six channels (a-f) has an associated open drain pup output that, when connected to a converter?s enable pin, controls the turn-on of the converter. the channels are assigned sequence positions to determine the order of the sequence. any channel can also be programmed to not take part in the sequencing in applications with fewer than six supplies. the polarity of each of the pup x outputs is programmable for use with various types of converters. power-on sequencing can be initiated by the pwr_on/off pin or via i 2 c control. the polarity of the pwr_on/off pin is programmable. if hard wired in its active state the smm665b will automatically initiate the power-on sequence. otherwise, toggling the pwr_on/off pin to its active state will initiate the power-on sequence. to enable software control of the sequencing feature, the smm665b offers an i 2 c command to initiate power-on sequencing while the pwr_on/off pin is in its inactive state. the smm665b can be programmed to wait until either or both vdd and 12vin inputs are within their respective voltage threshold limits before power-on sequencing is allowed to begin. this ensures that the converters have their full supply voltage before they are enabled. once power-on sequencing begins, the smm665b will wait a power-on delay time (t dpon ) for any channel in the first sequence position (0) and then activate the pup x outputs for those channels. the power-on delay times are individually programmable for each channel. the smm665b will then wait until all vm x inputs of the channels assigned to the first sequence position (0) are above their programmed uv1 thresholds which is called cascade sequencing. at this point, the smm665b will enter the second sequence position (1) and begin to timeout the power- on delay times for the associated channels. this process continues until all of channels in the sequence have turned on and are above their uv1 threshold. the status registers i ndicates that all sequenced power supply channels have turned on. once these channels are above their uv1 thresholds, the smm665b will begin the active dc control of the enabled channels. the power-on sequencing mode ends when the active dc controlled channels are at their nominal voltage setting. the ?ready? bit in the status registers signifies t hat the voltages are at their set points. the programmable sequence termination timer can be used to protect against a stalled power-on sequence. this timer resets itself at the beginning of each sequence position. all channels in the sequence position must go above their uv1 threshold before the sequence termination timer times out (t stt ) or the sequence will terminate and all pup x outputs will be switched to their inactive st ate. the status registers contain bits that indicate the sequence has been terminated and in which sequence position the timer timed out. this timer has four settings of off, 100ms, 200ms and 400ms. applications information (continued)
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 15 while the smm665b is in the power-on sequencing mode the rst output is held active and the healthy output is held inactive regardless of trigger sources (figure 8). the power-off and force shutdown trigger options are also disabled while in this mode. furthermore, the smm665b will not respond to activity on the pwr_on/off pin or to a power-off i 2 c command during power-on sequencing mode. ongoing operations-monitoring mode during ongoing operations mode, the part can (1) monitor (2) actively control via adoc, and (3) use force shutdown if necessary. once the power-on sequence is complete and before a power-off sequence has been initiated, the smm665b continues to monitor all vm x inputs, the vdd and 12vin inputs, and two temperature sensor inputs with a 10-bit adc. each of these inputs is sampled and converted by t he adc every 2ms. the adc input has a range of 0v to four times the voltage on vref_adc for inputs vm a-f and the vdd input. the range is extended to 12 times vref_adc for the 12vin input and is reduced to two times vref_adc for the ain1 and ain2 inputs. the smm665b monitors internal temperature using the 10-bit adc and the automonitor function. two under temperature and two over temperature thresholds can be set, each with its own programmable trigger options and consecutive conversion before trigger counter. resolution is 0.25 c per bit scaled over the range of -128 c to 127.75 c. the temperature value can be acquired over the i 2 c bus as a 10-bit signed two's complement value. the smm665b compares each resulting adc conversion with two programmable 10-bit under- voltage limits (uv1, uv2) and two programmable 10- bit over-voltage limits (ov1, ov2) for the corresponding input. a consecutive conversion counter is used to provide f iltering of the adc inputs. each limit can be programmed to require 1, 2, 4 or 6 consecutive out-of-limit conver sions before it is said to be in fault. one in-limit conversion will remove the fault from the threshold limit. this provides digital filtering of the monitored inputs. the adc inputs vm a- f can use additional filtering by connecting a capacitor from the corresponding cap x pins to ground to form an analog rc filter (r=25k ? ). the input is considered to be in a fault condition if any of its limit thresholds are in fault. setting an ov threshold limit to full-scale (3ff hex ), or setting an uv threshold limit to 000 hex ensures that the limit can never be in fault. the status registers provide the real-time status of all monitored inputs. the voltage threshold limits for inputs vm a-f , vdd and 12vin can be programmed to trigger the rst and healthy outputs as well as a force shutdown and power-off operation when exceeded. the threshold limits for the internal temperature sensor and the ain1 and ain2 inputs can be programmed to trigger the rst, healthy, and fault outputs. the healthy and fault outputs of the smm665b are active as long as the triggering limit remains in a fault condition. the rst output also remains active as long as the triggering limit remains in a fault condition; however, once the trigger source goes away the rst will remain active for a reset timeout period (t prto ). temperature sensor accuracy the internal temperature sensor accuracy is 5 o c from -40 to +90 o c. the sensor measures the temperature of the smm665b die and the ambient temperature. if vdd is at 5v, the die temperature is +2 o c and at 12v, it is +4 o c. in order to calculate this difference in specific applications measur e the vdd or 12vin supply current and calculate the power dissipated and multiply by 80 o c/w. for instance, 5v and 5ma is 25mw, which creates a 2 o c offset. margining the smm665b has two additional active dc output control voltage settings for channels a-f; margin high and margin low. the margin high and margin low voltage settings can range from 0.3v to vdd of the converters? nominal output voltage depending on the specified margin range of the dc-dc converter. these settings are stored in the configuration registers and are loaded into the active dc control voltage setting by margin commands issued via the i 2 c bus. the channel must be enabled for active dc control in order to enable margining. the margin command registers contain two bits for each channel that decode the commands to margin high, margin low, or control to the nominal setting. ther efore, any combination of margin high, margin low, and nominal control is allowed in the margining mode. once the smm665b receives the command to margin the supply voltages, it begins adjusting the supply voltages to move toward the desired setting. when all channels are at their voltage setting, a bit is set in the margin status registers. applications information (continued)
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 16 note: configuration writes or reads of registers 00 hex to 0f hex should not be performed while the smm665b is margining. power-off cascade sequencing the smm665b can be programmed to perform power- off sequencing in either the same order or reverse order of power-on cascade sequencing. power-off cascade sequencing can be initiated by the pwr_on/off pin, via i 2 c control or triggered by a fault condition on any of the monitored inputs. toggling the pwr_on/off pin to its inactive state will initiate the power-off sequence. to enable software control of the power-off sequencing feature, the smm665b offers an i 2 c command to initiate power-off sequencing regardless of the state of the pwr_on/off pin. furthermore, power-off sequencing can be initiated by a fault condition on a monitored input. once power-off sequencing begins, the smm665b will wait a power-off delay time (t dpoff ) for any channel in the last sequence position (reverse order) and then deactivate the pup outputs for those channels. the power-off delay times are individually programmable for each channel. the smm665b will then wait until all vm x inputs of the channels assigned to that sequence position are below the programmed off thresholds. at this point, the smm665b will decrement to the next sequence position and begin to timeout the power-off delay times for the associated channels. this process continues until all of channels in the sequence have turned off and are below their off thresholds. the status register reveal s that all sequenced channels have turned off. the power-off sequencing mode ends when all sequenced supplies are below their off thresholds. the programmable sequence termination timer can be used to protect against a stalled power-off sequence. this timer resets itself at the beginning of each sequence position. all channels in the sequence position must go below their off threshold before the sequence termination timer times out (t stt ) or the sequence will terminate and all pup outputs will be switched to their inactive state. this timer has four settings of off, 100ms, 200ms and 400ms. the sequence termination timer can be disabled separately for power-off sequencing. while the smm665b is in the power-off sequencing mode the rst output is held active and the healthy output is held inactive regardless of trigger sources (figure 8). the force shutdown trigger option is also disabled while in this mode. furthermore, the smm665b will not respond to activity on the pwr_on/off pin or to a power-on i 2 c command during power-off sequencing mode. force shutdown the force shutdown operation brings all pup x outputs to their inactive stat e. this operation is used for an emergency shutdown when there is not enough time to sequence the supplies off. the force shutdown operation shuts off all sequenced channels and waits for the supply voltages to drop below their respective off thresholds. a force shutdown operation can be initiated by any one of four events. the first two methods for initiating a force shutdown are always enabled. simply taking the fs pin to its active state will initiate a force shutdown operation and maintain it until the pin is brought to its inactive state. an i 2 c force shutdown command allows the force shutdown operation to be initiated via software control. this i 2 c force shutdown command sets a volatile register bit that triggers a force shutdown. this bit is cleared after all sequenced channels have dropped below their off voltage threshold. during power-on and power-off sequencing, the sequence termination timer can initiate a force shutdown operation. as described in the previous sections, the sequence termination timer triggers a force shutdown operation if it times out before the power supply voltages surpass their voltage thresholds. this force shutdown will remain active until all sequenced power supply channels have dropped below their off voltage threshold. while the smm665b is in ongoing operations-monitor mode, a programmed fault condition on any power supply channel or on the 12vin or vdd inputs can tri gger a force shutdown. a force shutdown resulting from this will remain active until all sequenced power supply channels have dropped below their off voltage threshold. for restarting the device, the fs command needs to be cleared by writing that bit to a zero. this will clear the command and, if the power-on/off pin is not being forced low externally the smm665b will begin a power-on sequence applications information (continued)
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 17 smm665 brownout recovery/handling during a power ?brown-out? (figure 9) the smm665b can default to a power-off state, thus requiring toggling of the pwr_on/off pin to enable the device to perform a power-on sequence. for applications using i 2 c control of the power-on/power-off function, the same result may be effected by, upon recovery of power, issuing a software (i 2 c) ?power-off? command followed by a ?power-on? command and ending with a ?clear? command. if the pwr_on/off pin is in the asserted state, the smm665b will initiate a power-on sequence once all input conditions are met. otherwise the pwr_on/off pin may require toggling if, upon recovery from the ?brownout?, it is in the de-asserted state. -48v supply 0v -48v smm665 supplies power brown-out vdd_cap +12vin smm665 hold-up time figure 9 - power brown-out with resulting loss of smm665b supply voltages applications information ( continued )
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 18 restart of power-on cascade sequencing once a force shutdown or power-off operation has completed, the smm665b can restart the power-on cascade sequencing. the device can be programmed to automatically restart after a force shutdown provided the pwr_on/off pin remains in the active state or the i 2 c power-on command remains in the command register. if this option is not selected, the smm665b requires toggling of the pwr_on/off pin or toggling of the i 2 c commands by issuing a power- off command and then reissuing the power-on command in order to restart power-on sequencing. in either case, assertion of the fs pin will prevent the smm665b from restarting power-on sequencing. in addition, the device can be programmed to check that vdd and the 12vin are within their programmed voltage thresholds before restarting power-on sequencing. in cases where brownout conditions (figure 10) or loss of power are used to cause a sequence off of the supplies or a force shutdown, it is best to toggle the pwr_on/off pin or use the i 2 c power commands after the brownout condition is over or if the supplies do not fully discharge before initiating a power-on sequence. recommended use of the pwr_on/off pin: the pwr_on/off pin is edge-triggered to lock out false or nuisance signals during both the power-on and power-off sequences. if during a system power- down, whether deliberate or due to a failed power system, the vdd_cap voltage falls below 2.5v, the smm665b internal uvlo (undervoltage lockout) circuit resets all internal logic. once power has recovered above 2.6v the smm665b will restart assuming the pwr_on/off pin is in the asserted state or an i 2 c power command is issued. the smm665b can be used with the pwr_on/off pin either toggled by a logic leve l, controlled by a software command or tied either high or low as described in the data sheet. vdd_cap 2.5v 3.6v, 5.5v uvlo (internal) 2.6v figure 10 - timing sequence recovering from a vdd_cap power ?brown-out? applications information ( continued )
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 19 figure 11 ? smm665b distributed power applications schematic. the accuracy of the external reference (u10) sets the accuracy of the adoc function. total accuracy with a 0.1% external reference is 0.2%. applications information ( continued ) smm665b
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 20 trim a vm a + trim b vm b + smm665b ir ip1202 vsw1 sda scl i2c bus vreg_in 12v 12v cs vin fb1 vout1 1.5v fb1s rtrim 1.6k vsw2 fb2 vout2 2.5v fb2s rtrim 3.3k not all components shown for interface purposes only part designators are from the international rectifier ip1202 demo board . ss2 pup a ss1 pup b r9 r7 c8 c7 r10 r8 figure 12 ? the smm665b can be used to sequence and control discrete dc switching regulators. the adoc function sets the output voltage of the ir ip1202 regul ator through the fbx feedback pins. accuracy is improved even under full load, essentially acting as a ?sense? pin. the sequence function is applied through the ip1202 ssx soft start pins. figure 13 ? ch1 is set to 2.5v and ch2 is set to 1.5v on the ip1202 board. ch1 is set to sequence on first followed by ch2 after 50ms. then ch1 is margined high while ch2 is margined low. ch2 is then sequenced off followed by ch1 after 50ms. figure 14 ? this is the same sequencing-on function but with a shorter delay between channels, the healthy and reset flags are also shown. applications information ( continued )
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 21 the end user can obtain the summit smx3200 programming system for device prototype development. the smx3200 system consists of a programming dongle, cable and windows tm gui software. it can be ordered on the website or from a local representative. the smx3200 programming dongle/cable interfaces directly between a pc?s parallel port and the target application. the device is then configured on-screen via an intuitive graphical user interface employing drop-down menus. the windows gui software will generate the data and send it in i 2 c serial bus format so that it can be directly downloaded to the smm665b via the programming dongle and cable. an example of the connection interface is shown in figure 15. when design prototyping is complete, the software can generate a hex data file that should be transmitted to summit for approval. summit will then assign a unique customer id to the hex code and program production devices bef ore the final electrical test operations. this will ensure proper device operation in the end application. the latest revisions of all software and an application brief describing the smx3200 is available from the website at: http://www.summitmicro.com/tech_s upport/program_kit/smx3200.htm pin 9, 5v pin 7, 10v pin 5, reserved pin 3, gnd pin 1, gnd pin 6, mr# pin 4, sda pin 2, scl pin 8, reserved pin 10, reserved top view of straight 0.1" x 0.1 closed-side connector. smx3200 interface cable connector. 9 7 5 3 1 10 8 6 4 2 smm665b sda scl vdd_cap gnd 0.1 f mr d1 1n4148 figure 15 ? smx3200 programmer i 2 c serial bus connections to program the smm665b. note that the mr pin does not need to be connected to pin 6 for programming purposes. development hardware & software
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 22 serial interface access to the configurati on registers, general-purpose memory and command and status registers is carried out over an industry standard 2-wire serial interface (i 2 c). sda is a bi-directional data line and scl is a clock input. data is clocked in on the rising edge of scl and clocked out on the falling edge of scl. all data transfers begin with the msb. during data transfers sda must remain stable while scl is high. data is transferred in 8-bit packets with an intervening clock period in which an acknowledge is provided by the device receiving data. the scl high period (t high ) is used for generating start and stop conditions that precede and end most transactions on the serial bus. a high-to-low transition of sda while scl is high is considered a start condition while a low-to-high transition of sda while sc l is high is considered a stop condition. the interface protocol allows operation of multiple devices and types of devices on a single bus through unique device addressing. the address byte is comprised of a 4-bit device type identifier (slave address) and a 3-bit bus address. the remaining bit indicates either a read or a write operation. refer to table 1 for a description of the address bytes used by the smm665b. the device type identifier for the memory array is generally set to 1010 bin following the industry standard for a typical nonvolatile memory. there is an option to change the identifier to 1011 bin allowing it to be used on a bus that may be occupied by other memory devices. the configuration registers are grouped with the memory array and thus use 1010 bin or 1011 bin as the device type identifier. the command and status registers as well as the 10-bit adc are accessible with the separate device type identifier of 1001 bin . the bus address bits a[1:0] are programmed into the configuration registers. bus address bit a[2] can be programmed as either 0 or biased by the a2 pin. the bus address accessed in the addr ess byte of the serial data stream must match the setting in the smm665b and on the a2 pin. any access to the smm665b on the i 2 c bus will temporarily halt the monitoring function. this does not affect the adoc function, which will continue functioning and control the dc outputs. this is true not only during the monitor mode, but also during power-on and power-off sequencing when the device is monitoring the channels to determine if they have turned on or turned off. the smm665b halts the monitor function from when it acknowledges the address byte until a valid stop is received. write writing to the memory or a configuration register is illustrated in figures 16, 17, 19, 21 and 22. a start condition followed by the address byte is provided by the host; the smm665b responds with an acknowledge; the host then responds by sending the memory address pointer or configuration register address pointer; the smm665b responds with an acknowledge; the host then clo cks in on byte of data. for memory and configuration register writes, up to 15 additional bytes of data can be clocked in by the host to write to consecutive addresses within the same page. after the last byte is clocked in and the host receives an acknowledge, a stop condition must be issued to initiate the nonvolatile write operation. read the address pointer for the configuration registers, memory, command and status registers and adc registers must be set before data can be read from the smm665b. this is accomplished by a issuing a dummy write command, which is simply a write command that is not followed by a stop condition. the dummy write command sets the address from which data is read. after the dummy write command is issued, a start command followed by the address byte is sent from the host. the host then waits for an acknowledge and then begins cl ocking data out of the slave device. the first byte read is data from the address pointer set during the dummy write command. additional bytes can be clo cked out of consecutive addresses with the host providing an acknowledge after each byte. after the data is read from the desired registers, the read operation is terminated by the host holding sda high during the acknowledge clock cycle and then issuing a stop condition. refer to figures 18, 20 and 23 for an illustration of the read sequence. i 2 c programming information
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 23 write protection the smm665b powers up into a write protected mode. writing a code to the volatile write protection register can disable the write protec tion. the write protection register is located at address 87 hex of slave address 1001 bin . writing 0101 bin to bits [7:4] of the write protection register allow writes to the general-purpose memory while writing 0101 bin to bits [3:0] allow writes to the configuration registers. the write protection can re- enable by writing other codes (not 0101 bin ) to the write protection register. writing to the write protection register is shown in figure 16. configuration registers the majority of the confi guration registers are grouped with the general-purpose memory located at either slave address 1010 bin or 1011 bin . the bus address bits, a[1:0], used to diffe rentiate the general-purpose memory from the configuration registers are set to 11 bin . bus address bit a[2] can be programmed as either 0 or biased by the a2 pin. two additional configuration registers are located at addresses 83 hex and 84 hex of slave address 1001 bin . writing and reading the configuration registers is shown in figures 17, 18, 19, 20 and 21 note: configuration writes or reads of registers 00 hex to 0f hex should not be performed while the smm665b is margining. general-purpose memory the 4k-bit general-purpose memory is located at either slave address 1010 bin or 1011 bin . the bus address bits, a[1:0], used to differentiate the general- purpose memory from the c onfiguration registers are set to 00 bin for the first 2k-bits and 01 bin for the second 2k-bits. bus address bit a[2] can be programmed as either 0 or biased by the a2 pin. the word address must be set each time the memory is accessed. memory writes and reads are shown in figures 22, 23 and 24. command and status registers the command and status registers are located at slave address 1001 bin . writes and reads of the command and status registers are shown in figures 25 and 26. adc conversions an adc conversion on any monitored channel can be performed and read over the i 2 c bus using the adc read command and requires 182 s to complete. the adc read command, shown in figure 27, starts with a dummy write to the 1001 bin slave address. bits [6:3] of the word address byte are used to address the desired monitored input. once the device acknowledges the channel addr ess, it begins the adc conversion of the addressed input. this conversion requires 70 s to complete. during this conversion time, acknowledge polling can be used. the smm665b will not acknowledge the address bytes until the conversion is complete. when the conversion has completed, the smm665b will acknowledge the address byte and return the 10-bit conversion along with a 4-bit channel address echo. graphical user interface (gui) device configuration utilizing the windows based smm665b graphical user interface (gui) is highly recommended. the software is available from the summit website at: ( http://www.summitmicro.com/tech_support/tech.htm# gui . using the gui in conjunction with this datasheet and application note 33, simplif ies the process of device prototyping and the interaction of the various functional blocks. a programming dongle (smx3200) is available from summit to communicate with the smm665b. the dongle connects directly to the parallel port of a pc and programs the device through a cable using the i 2 c bus protocol. slave address bus address register type 1001 bin a2 a1 a0 write protection register, command and status registers, two configuration registers, adc conversion readout a2 0 0 1 st 2-k bits of general-purpose memory a2 0 1 2 nd 2-k bits of general-purpose memory 1010 bin or 1011 bin a2 1 1 configuration registers i 2 c programming information (continued)
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 24 table 1 - address bytes used by the smm665b. s t a r t w a c k master slave a c k configuration register address = 87 hex 1 0000111 0 1010101 s t o p data = 55 hex a c k 1 0 0 1 a 2 bus address a 1 a 0 5 hex unlocks general purpose ee 5 hex unlocks configuration registers write protection register address 8 hex 7 hex figure 16 ? write protection register write s t a r t 1 a 2 bus address w a c k master slave a c k 1 1 0 1 s a 0 configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p data a c k figure17 ? configuration register byte write s t a r t 1 a 2 bus address w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p master master slave slave a c k data (16) 1 1 0 1 s a 0 configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (2) a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k figure 18 ? configuration register page write i 2 c programming information (continued)
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 25 s t a r t 1 a 2 bus address w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k master master slave slave a c k data (n) 1 1 0 1 s a 0 configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 s t a r t 1 r a c k a 2 bus address 1 1 s a 0 0 1 a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) figure 19 - configuration register read s t a r t w a c k master slave a c k configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p data a c k 1 0 0 1 a 2 bus address a 1 a 0 figure 20 - configuration register with slave address 1001 bin write s t a r t w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k master master slave slave a c k data (n) configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 s t a r t r a c k a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) 1 0 0 1 a 2 bus address a 1 a 0 1 0 0 1 a 2 bus address a 1 a 0 figure 21 - configuration register with slave address 1001 bin read i 2 c programming information (continued)
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 26 s t a r t 1 bus address w a c k master slave a c k 0 1 s a 0 memory address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p data a c k 0 a 2 0 / 1 figure 22 ? general purpose memory byte write bus address 0 a 2 0 / 1 s t a r t 1 w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p master master slave slave a c k data (16) 0 1 s a 0 memory address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (2) a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k figure 23 - general purpose memory page write s t a r t 1 w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k master master slave slave a c k data (n) 0 1 s a 0 memory address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 s t a r t 1 r a c k 1 s a 0 0 a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) bus address 0 a 2 0 / 1 bus address 0 a 2 0 / 1 figure 24 - general purpose memory read i 2 c programming information (continued)
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 27 s t a r t w a c k master slave a c k command and status register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p data a c k 1 0 0 1 a 2 bus address a 1 a 0 figure 25 ? command and status register write s t a r t w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k master master slave slave a c k data (n) command and status register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 s t a r t r a c k a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) 1 0 0 1 a 2 bus address a 1 a 0 1 0 0 1 a 2 bus address a 1 a 0 figure 26 - command and status register read s t a r t 1 0 0 1 a 2 bus address a 1 a 0 w c h 3 c h 2 c h 1 c h 0 a c k s t a r t 1 0 0 1 a 2 bus address a 1 a 0 r s t a r t 1 0 0 1 a 2 bus address a 1 a 0 r c h 3 c h 2 c h 1 c h 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k n a c k master master slave slave channel address echo channel address 0 0 0 0 a c k 10-bit adc data a c k a c k 0 0 figure 27 ? adc conversion read i 2 c programming information (continued)
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 28 default configuration register settings ? smm665bfc-266 register contents register contents register contents register contents r0 0d r40 0d r98 41 rbf e0 r1 83 r41 b9 r99 3e rc0 0b r2 0d r42 0e r9a 81 rc1 38 r3 ff r43 39 r9b 33 rc2 0b r4 0e r44 0e r9c 29 rc3 38 r5 61 r45 a4 r9d 9a rc4 09 r6 0e r46 0f r9e 11 rc5 90 r7 c7 r47 16 r9f ae rc6 09 r8 0f r48 0f ra0 41 rc7 90 r9 54 r49 b4 ra1 0b rc8 0c ra 0b r4a 06 ra2 80 rc9 00 rb 22 r4b 7f ra3 f6 rca 0c rc 7f r4c 00 ra4 29 rcb 00 rd 3f r4d 12 ra5 5d rcc 0f re 03 r4e 50 ra6 11 rcd ff rf 01 r80 42 ra7 71 rce 0f r10 8f r81 48 ra8 40 rcf ff r11 9f r82 82 ra9 ce rd0 0c r12 af r83 3e raa 80 rd1 00 r13 bf r84 2a rab 8f rd2 0c r14 cf r85 b8 rac 29 rd3 00 r15 df r86 12 rad 1f rd4 0f r18 00 r87 f6 rae 11 rd5 d8 r19 00 r88 41 raf 33 rd6 0f r30 0d r89 c8 rb0 2a rd7 d8 r31 60 r8a 81 rb1 67 re0 00 r32 0d r8b b9 rb2 0a re1 3d r33 dc r8c 2a rb3 52 re2 00 r34 0e r8d 34 rb4 03 re3 3d r35 45 r8e 12 rb5 ff re4 00 r36 0e r8f 49 rb6 03 re5 3d r37 a2 r90 49 rb7 ff re6 00 r38 0f r91 5c rb8 0d re7 3d r39 08 r92 81 rb9 9a re8 00 r3a 0f r93 52 rba 0d re9 3d r3b d6 r94 29 rbb 56 rea 00 r3c 00 r95 d7 rbc 0f reb 3d r3d 12 r96 11 rbd e0 r3e 50 r97 eb rbe 0f rc1 the default device ordering number is s mm665bfc-266. it is programmed with t he register contents as shown above and tested over the commercial temperature range with a default vref setting of 1.25v. other standard external vref voltage settings that can be specified and tested ar e values of: 1.024, 1.225, 1.250, 2.048, 2.500, 3.000 or 3.300. the value is derived from the customer suppli ed hex file. new device suffix numbers are assigned for all non- default vref requirements. if other vref values are required, please contact a summit microelectronics sales representative. application note 33 contains a complete description of the windows gui and the default settings of each of the 154 individual configuration registers.
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 29 package a b pin 1 indicator inches (millimeters) 0.002 - 0.006 (0.05-0.15) max. 0.047 (1.2) 0.037 - 0.041 0.95 - 1.05 0.018 - 0.030 (0.45 - 0.75) 0.039 (1.00) 0.02 (0.5) bsc 0.007 - 0.011 (0.17 - 0.27) detail "a" detail "b" (b) (a) (a) 0.354 (9.00) bsc 0.276 (7.00) bsc (b) 48 pin tqfp package 0 o min to 7 o max ref jedec ms-026 ref
smm665b preliminary information summit microelectronics, inc 2089 2.0 4/11/2007 30 part marking ordering information notice note 1 - this is a preliminary information data sheet that describes a summit product currently in pre-production with limited characterization. revision 2.0 - this document supersedes all previous versions. data sheet updates c an be accessed by ?right? or ?left? mouse c licking on the link: http://www.summitmicro.com/prod_s elect/summary/smm665/smm665.htm device errata sheets can be accessed by ?right? or ?l eft? mouse clicking on the link: http://www.summitmicro.com/errata/smm665b summit microelectronics, inc. reserves the right to make changes to the products cont ained in this publication in order to impr ove design, performance or reliability. summit microelec tronics, inc. assumes no responsibility for the use of any circuits described herei n, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and sche dules contained herein reflect representative operating par ameters, and may vary depending upon a user?s specific application. while the inform ation in this publication has been carefully checked, summi t microelectronics, inc. shall not be liabl e for any damages arising as a result o f any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expec ted to cause any failure of either syst em or to significantly affect their sa fety or effectiveness. products are not authorized for use in such applications unless summit microelectronics, in c. receives written assurances, to i ts satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the us er assumes all such risks; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. ? copyright 2006 summit microelectronics, inc. programmable power for a digital world? adoc tm is a registered trademark of summit microelectronics inc., i 2 c is a trademark of philips corporation. summit smm665bf ayyww pin 1 annn summit part number date code (yyww) part number suffix (contains customer specific programming and ordering requirements. the default device ordering number is not marked on the device) lot tracking code (summit use) drawing not to scale xx status tracking code (blank, ms, es, 01, 02,...) (summit use) product tracking code (summit use) l 100% sn, rohs compliant smm665b f package f=48 lead tqfp summit part number specific requirements are contained in the suffix such as hex code, hex code revision, etc. the calibrated vref voltage settings are standard values of: 1.024, 1.225, 1.250, 2.048, 2.500, 3.000 or 3.300 nnn part number suffix (see page 28) c temp range c=commercial blank=industrial l environmental attribute

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